Logic Design and Verification Using SystemVerilog - Donald Thomas
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Saadetis 10-16 tööpäeva jooksul
30-päevane tagastamisõigus
SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: * students currently in an introductor ... Täielik kirjeldus
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Kirjeldus
Lisateave
| Autor | Donald Thomas |
|---|---|
| Kirjastaja | CreateSpace Independent Publishing Platform |
| Väljalaskeaasta | 2016 |
| Kaanetüüp | Pehme kaanega |
| EAN | 9781523364022 |