Raamatud S. Sapatnekar
Timing Analysis and Optimization of Sequential Circuits
S. Sapatnekar, Naresh Maheshwari
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Design Automation for Timing-Driven Layout Synthesis
Sung-Mo (Steve) Kang, S. Sapatnekar
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Designing Digital Computer Systems with Verilog
David J. Lilja, Sachin S. Sapatnekar
-30% koodiga BOOKS
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Designing Digital Computer Systems with Verilog
David J. Lilja, Sachin S. Sapatnekar
-30% koodiga BOOKS
Meie tarnija laos
Timing Analysis and Optimization of Sequential Circuits
S. Sapatnekar, Naresh Maheshwari
-30% koodiga BOOKS
Meie tarnija laos
Design Automation for Timing-Driven Layout Synthesis
S. Sapatnekar, Sung-Mo (Steve) Kang
-30% koodiga BOOKS
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Electromigration Inside Logic Cells Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis
-30% koodiga BOOKS
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Electromigration Inside Logic Cells Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis
-30% koodiga BOOKS
Meie tarnija laos